design planning implementation integration and verification, haveli (maharashtra) , deadline is 14 aug 2026
| design, planning, implementation, integration, and verification of four 100 g ethernet ip blocks on stratix 10 rxpu fpga for synchronized multi-slice band 4.5 a. 5 b data transfer | |
| Deadline | 14 aug 2026 |
| Tenders Location | haveli - maharashtra |
| Tenders Value | Refer Document |
| Document Cost | Refer Document |
| Tender categeory | electronics, telecom |
| Our Ref. ID | 260801425650 |
| Download Tender Document | |
